Yes. Please refer to the following programming guides:

• RF205x Quick Start Guide
• Integrated Synthesizer/Mixer Programming Guide
• Integrated Synthesizer/Mixer/Modulator Family Register Map Description
• IQ Modulator Programming Guide

There are a number of things that could be happening. This FAQ contains solutions for the most common problems. To aid in troubleshooting, we have produced a fault finding guide for the RF205x.

The software and FTDI USB drivers are available from the RFMD Integrated Synthesizer/Mixer and Integrated Synthesizer/Modulator web pages under the “GUI Software Tools” and “FTDI USB Driver” headings.

Before installing a new version of the Slice programming tool, remove older versions via Control Panel > Add or Remove Programs facility.

The files are compressed into .zip archives. After extracting the files, run setup.exe to create all necessary folders and install the software.

The USB-to-serial adaptor on the RF205x evaluation boards is the FTDI UM232R. It is programmed with a configuration file at RFMD. The USB drivers from FTDI need to be installed prior to using the evaluation boards and programming tool. They can be found here.

Information about Windows, Linux, and Mac drivers can be found on the FTDI website.

Instructions on programming the FTDI device can be found in the Eval Board & Programming Tool Guide for Mixers & Modulators with Integrated Synthesizers.

Additionally, download the programming file.

There are a couple of alternative methods of programming RFMD’s Integrated Synthesizer products:

1. Write your own code. Information about the FTDI drivers can be found here for Windows, Linux, and Mac.
2. Use Excel with the files provided here.
3. Use the PC loader, only available internally.

Further information on programming the device from within Excel is available in this document. An example spreadsheet can be found here.

Yes. The following is an example of how to structure code for programming the device.

initialisation () // initialise control pins
{
    RESETB = 0;
    ENX = 1;
    SCLK = 0;
    SDATA = 0; //Set SDATA as output
    ENBL = 0;
    wait(100ns); // ensure reset is complete
    RESETB = 1;
}
send_address ( R_W, addr )
{
    SCLK = 1; // send initial clock pulse
    wait(30ns);
    SCLK = 0;
    ENX = 0; // start read or write operation
    SCLK = 1;
    wait(30ns);
    SCLK = 0;
    if R_W = "write" // set read or write flag
    {
        SDATA = 0;
        wait(30ns);
        SCLK = 1;
        wait(30ns);
        SCLK = 0;
    }
    else
    {
        SDATA = 1;
        wait(30ns);
        SCLK = 1;
        wait(30ns);
        SCLK = 0;
    }
    count = 0;
    while ( count < 7 )
    {
        // extract data bit from address and send to device
        if ( addr & ( 0x40 >> count ) )
        {
            SDATA = 1;
            wait(30ns);
            SCLK = 1;
            wait(30ns);
            SCLK = 0;
        }
        else
        {
            SDATA = 0;
            wait(30ns);
            SCLK = 1;
            wait(30ns);
            SCLK = 0;
        }
        count++;
    }
    if R_W = "read" // if reading device insert extra clock edges
    {
        wait(30ns);
        SCLK = 1;
        Set SDATA as input
        wait(30ns);
        SCLK = 0;
        wait(30ns);
        SCLK = 1;
    }
}
send_data ( data )
{
    count = 0;
    while ( count < 16 )
    {
        // extract bit from data and send to device
        if ( data & ( 0x8000 >> count ) )
        {
            SDATA = 1;
            wait(30ns);
            SCLK = 1;
            wait(30ns);
            SCLK = 0;
        }
        else
        {
            SDATA = 0;
            wait(30ns);
            SCLK = 1;
            wait(30ns);
            SCLK = 0;
        }
        count++;
    }
    ENX = 1; // transmission complete
    wait(30ns);
    SCLK = 1; // tidy up clock
    wait(30ns);
    SCLK = 0;
}
receive_data () // SDATA must be defined as input
{
    count = 0;
    read_data = 0;
    while ( count < 16 )
    {
        // build data word, MSB read back first
        wait(30ns);
        SCLK = 0;
        read_data = (RX_data * 2) + SDATA
        wait(30ns);
        SCLK = 1;
        count++;
    }
    ENX = 1; // reception complete
    wait(30ns);
    SCLK = 0; // tidy up clock
    Set SDATA as output
    return read_data
}
set_path ( path )
{
    MODE = path - 1;
}
enable_chip ()
{
    ENBL = 1;
}

• Set the charge pump leakage (CPL) setting to 01. This lowers close-in phase noise by about 2dB.
• Increase charge pump current. This also lowers close-in phase noise, and widens the loop bandwidth.
• Use a higher phase detector frequency to minimize N and noise multiplication in the PLL, 20log₁₀N.
• Select the VCO that’s at the low end of the tuning range, where possible. For example at 2GHz you could use VCO1 or VCO2, but VCO1 has lower phase noise at this frequency.
• Set LDO_BYP to 1 in TEST register. This can improve VCO phase noise, as long as the power supply is from a low noise source.
• A passive loop filter gives slightly lower phase noise at around 100kHz offset, since there is no noise contribution from the op-amp used in the active loop filter. Plots in the data sheet demonstrate this. You do need to be more careful about VCO coarse tune calibration though, see questions below on CT_CAL for further details.
• Setting the correct loop bandwidth is important to obtain the lowest integrated phase noise. Typically 100KHz for a 26MHz crystal reference.

If one of the mixer input pins is connected to DC ground then the mixer becomes unbalanced and the LO signal is routed to the mixer output. The level will be around +3dBm ±3dB, depending on frequency.

The fractional-N divider is controlled by a sequence generator, a form of sigma delta modulator known as a MASH. This effectively takes the spurs seen on a traditional fractional-N synthesizer caused by the N/N+1 switching and pushes them outside the loop bandwidth as random noise. The fractional divider does not put spurs on the LO as such, but a small noise contribution at 100kHz to 1MHz offset which is attenuated by the loop filter.

One type of fractional spur that can be present at certain frequencies are integer N boundary spurs, and these are often used to analyze the performance of fractional N synthesizers. These are spurs that occur when the VCO is programmed close to an integer multiple of the reference frequency.

The integer N boundary spurs for these devices are typically below -55dBc.

The VCO coarse tuning or VCO band selection basically switches capacitors into the VCO resonator until it is centered at the required frequency. This calibration is enabled by default, and is performed after the ENBL pin is raised. After calibration, the PLL locking begins. The coarse tuning calibration can be disabled, for example to speed up lock time, but the value of the CT_CAL for the required VCO frequency needs to be written to the device.

The loop filter or Kv calibration is disabled by default, and is not required in the majority of applications. This calibration varies the charge pump current to compensate for changes in Kvco (MHz/V) and N with different LO frequencies. It is only necessary in applications where the VCO is tuned over a wide frequency range and the loop response needs to be tightly controlled.

This depends on what calibrations are enabled, the clock (phase detector) frequency, and the loop bandwidth. Different applications will also have different definitions of the locking time. Typically with a 26MHz clock, 60kHz loop bandwidth, and CT_CAL enabled, the lock time will be approximately 100µsecs after ENBL is taken high. If CT_CAL is disabled, then the typical lock time will be reduced to approximately 70µsecs.

By widening the loop bandwidth the lock time can be reduced further, but this does have an effect on phase noise.

An application note on reducing lock time is available from the RFMD web site.

The reference frequency, or phase detector frequency after the reference divider, will affect the phase noise within the loop bandwidth. Using a different phase detector frequency affects the divider value N and the amount of noise multiplication in the loop. With a lower phase detector frequency the higher phase noise will be. The noise is proportional to N², since it follows 20log₁₀(N) law, until the phase detector frequency reaches 40MHz where the synthesizer noise floor begins to increase. The following table shows some examples for a 1600MHz local oscillator frequency using the evaluation board:

The phase detector frequency is also used as the clock for the synthesizer calibrations, so will also affect lock time. A lower clock frequency will increase the lock time. In some circumstances it is necessary to adjust internal timer values to account for this.

The lowest frequency VCO on the RF205x series parts uses an external inductor in the tank circuit. The frequency is tuned using the internal variable capacitors. For correct biasing the center of the inductor must be connected to ground, this is possible since the oscillator is a balanced design and the center of the inductors is a virtual earth.

The inductance can be calculated from the standard formula for the resonant frequency of a tuned circuit:

• f is the resonant frequency,
• L is the external inductance, and
• C is the internal capacitance (2.2pF to 5pF)

When trying to achieve a continuous tuning range of 1200 to 2500MHz VCO3 needs to tune from 1200MHz to more than 1600MHz. In this case the total inductance must be approximately 4nH. This is split into two halves and the bondwire and via inductance subtracted to leave 1nH for each external inductor track. The RF205x Synthesizer User Guide includes details of how to calculate the inductor value for VCO3.

If a lower frequency VCO is required then the inductance value can be increased. If the inductance value is increased beyond ≈10nH a parallel resistor should be placed across the VCO port to reduce the circuit Q to an acceptable value. Further details can be found in the RF2056 Frequency Synthesizer User Guide. Also see next section.

The VCO frequency ranges specified in the data sheet are conservative to allow margin for process, assembly, and temperature variations. They are the guaranteed frequency ranges. The VCOs may operate outside of these ranges, for example it may be possible to lock VCO1 at 2600MHz. The specified frequency ranges given are also for optimum phase noise and tuning gain, K_VCO.

It is possible to tune VCO3 outside of the normal guaranteed frequency range of 1200MHz to 1600MHz by changing the external inductors. The maximum possible frequency will be when the pins are directly shorted to ground, so the resonator inductance is about 0.5nH on each pin from the inductance of the device bond wires. For lower VCO frequencies, lumped high Q inductors could be used. Again the performance of VCO3 is not guaranteed outside of the specified frequency range. For applications requiring LO frequencies below 300MHz we recommend using the RF2056.

The RF2056 uses external inductors on the VCO resonator, and the LO is specified to operate from 50MHz to 500MHz (200MHz to 500MHz VCO range). This is dependent on the value of external inductors used on the VCO, and the LO divider setting. The on-chip capacitor varies from approximately 2.8pF to 6.1pF in 0.26pF steps (CT_CAL value).

For a single inductor value the recommended maximum tuning range is approximately 40% (200MHz to 280MHz) allowing for tolerances and part-to-part variation (total tuning range of ∼50% is possible but would not leave any allowance for tolerancing so is not recommended for production).

1. Determine the VCO frequency range (between 200MHz and 500MHz)
2. Calculate the geometric mean frequency F_m = (F_MINF_MAX)½
3. Using the central capacitance value of C_m = 4.1pF calculate the required inductance by rearranging the standard formula F_m=1/(2π(L_mC_m)^½ ), for example, L_m=1/(C_m(2πF_m)²)

Since the inputs are balanced, the inductor has to be split in half. The required inductance in each arm is L=L_m/2. A standard value inductor, together with a length of PCB trace, can be used to obtain the correct value.

For example, to get a VCO range of 200MHz to 280MHz:

• F_m = (200*280)^½ = 237MHz
• L_m = 1/(4.1e-12*(2π237M)²) = 110nH
• L = 55nH

More information and some plots can be found in the RF2056 Frequency Synthesizer User Guide.

The integrated op-amp on the RF2053 can be used, but it is not recommended for two reasons. The op-amp output voltage range is only about +0.2V to +2.4V, which is not sufficient for the tuning range of most external VCOs. The noise performance of the op-amp is not low enough to give the full benefit of the low phase noise performance offered by an external VCO.

When the ENBL pin is set to High, the VCO coarse tuning calibration (CT_CAL) adjusts the VCO switched capacitance until the VCO is on the correct frequency and the VCO tuning voltage is around +1.1V. This is in the middle of the op-amp output voltage range of approximately +0.2V to +2.4V.

The lock detect function uses a window detector, indicating an out of lock condition when the VCO tuning voltage is outside of a certain voltage range. When out of lock, then the LOCK bit (bit 1 in the readback register RB1) will be High. It is possible that when an out of lock is indicated, the PLL is still locked but the tuning voltage is outside of the range of the window detector.

There are two windows for the lock detector:

• LD_LEV=0: 0.55V to 1.60V (narrow window)
• LD_LEV=1: 0.33V to 1.81V (wide window)

The two lock detector windows can be useful to indicate how much the VCO is drifting, and when it will be necessary to perform another CT_CAL. If with LD_LEV = 0 you get an out of lock state, this would probably indicate that the PLL is still locked, but the VCO and tuning voltage has drifted somewhat with temperature variation. This is confirmed if you get a lock indicated with LD_LEV = 1. Perform a CT_CAL to recenter the VCO.

If you get an out of lock indicated with both LD_LEV = 0 and 1, then either there is no PLL lock, or you are dangerously close to the tuning range limits. Perform a CT_CAL, by disabling and re-enabling the device.

Note that the LOCK detect function will not work with the RF2053 and external VCO’s. However a similar window detector could be used on the external VCO tuning line for example by using comparators.

When CT_CAL has been successful, the PLL has locked, and the CT_CAL result is available in the read back register RB1. This can be useful for diagnostics since the expected CT_CAL value (0 to 127) for the programmed VCO frequency can be compared to the read back result. There is a plot of typical CT_CAL results versus VCO frequency in the RF205x Calibration User Guide.

In time-switched applications this is not an issue since VCO coarse tuning is performed every time one of the mixers is enabled. For applications where the device is always on, the question is raised of how often to perform the coarse tune calibration. Testing the RF205x devices over temperature has shown that the synthesizer will maintain lock over the full temperature range, with the same CT_CAL setting. This includes the worst case of performing the CT_CAL at one temperature extreme, then taking the device to the other extreme. It is recommended you perform the CT_CAL for every 30°C temperature change in order to maintain the loop response and maximize performance. This assumes the standard configuration with the active loop filter.

In the case of using a passive loop filter it is recommended you perform the CT_CAL for every 10°C temperature change. This is because the charge pump output voltage range is significantly less than that of the op-amp, so any change in tuning voltage due to VCO frequency drift needs to be minimized

The XTAL pins 10 and 11 are differential, so an external reference can be fed into either pin, AC-coupled. The other pin needs to be AC-coupled to ground. Whatever makes PCB routing easier.

If the device has a crystal attached it is possible to minimize the LO frequency error by using the crystal tuning register settings. The crystal oscillator contains fixed and variable loading capacitors that can be used to tune the crystal. The amount of tuning possible will depend on the crystal specification.

A typical crystal frequency error spec will be around 10ppm.

If an external TCXO is being used this should be tuned to the correct frequency using the tuning input, typically a TCXO will have a frequency error of a few ppm at room temperature.

In some modes of operation the fractional-N sequence generator also causes a slight frequency offset or half an LSB (typically <0.005ppm).

• Increase charge pump current. This also lowers close-in phase noise, and widens the loop bandwidth.
• Use a higher phase detector frequency to minimize N and noise multiplication in the PLL, 20log₁₀N.
• Set RGBYP to 1 in TEST register, to bypass the on-chip LDO that supplies the VCOs. This can improve VCO phase noise, as long as the power supply is from a low noise source.
• Setting the correct loop bandwidth is important to obtain the lowest integrated phase noise. Typically 100KHz for a 26MHz reference, and 200KHz for a 52MHz reference.
• Use prescaler setting of /2 for lowest phase noise.*

* For VCO frequencies above 3200MHz the prescalar needs to be set to /4 during the CT_CAL process. After calibration is completed the prescaler will need to be reprogrammed to /2 for lowest phase noise. See programming guide for further details.

For the RFFC207x and RFFC507x devices with integrated mixers there is a register setting to allow access to the LO signal. If the BYPAS bit in the DEV_CTRL register is set high then the mixer becomes unbalanced and the LO signal is routed to the mixer output. The level will be around +3dBm ∓3dB, depending on frequency.

For the RFMD208x devices with integrated IQ modulator then voltages must be applied to the baseband I and Q inputs to maximize the LO signal at the modulator output. The recognized method is to replace the baseband AC signal with DC voltages that can be thought of as viewing baseband sine/cosine signals at a frozen instance in time. The DC voltages must be chosen carefully to get the correct output power and noise, and the recommended levels are:

• 0.941V to I_n and Q_p (pins 22 and 19)
• 0.659V to I_p and Q_n (pins 23 and 18)

These DC voltages need to be low noise.

The fractional-N divider is controlled by a sequence generator, a form of sigma delta modulator known as a MASH. This effectively takes the spurs seen on a traditional fractional-N synthesizer caused by the N/N+1 switching and pushes them outside the loop bandwidth as random noise. The fractional divider does not put spurs on the LO as such, but a small noise contribution at 100kHz to 1MHz offset which is attenuated by the loop filter.

One type of fractional spur that can be present at certain frequencies are integer N boundary spurs, and these are often used to analyze the performance of fractional N synthesizers. These are spurs that occur when the VCO is programmed close to an integer multiple of the reference frequency.

The integer N boundary spurs for these devices are typically below -55dBc.

The VCO coarse tuning or VCO band selection basically switches capacitors into the VCO resonator until it is centered at the required frequency. This calibration is enabled by default, and is performed after the ENBL pin is raised. After calibration, the PLL locking begins. The coarse tuning calibration can be disabled, for example to speed up lock time, but the value of the CT_CAL for the required VCO frequency needs to be written to the device.

There are three VCOs covering the frequency range 2.7 to 5.4GHz. The VCO Auto Select process forms part of the VCO coarse tuning, and it selects the correct VCO for the programmed VCO frequency after the device is enabled. The VCO coarse tuning calibration is run across each VCO in turn, until the correct VCO and CT_CAL value are determined. The process starts on the VCO number programmed into P1VCOSEL/P2VCOSEL in the P1_FREQ1 and P2_FREQ2 registers. So programming the correct VCO can reduce the time for the calibrations to run before the PLL locks.

The VCO Auto Select process is enabled by default. It can be disabled, but this is not recommended especially when operating close to the VCO cross over points. With process variation the exact overlap frequency between VCOs can not be guaranteed.

It is recommended to program P2VCOSEL = 00 in P2_FREQ1 register to ensure that the VCO auto select starts on VCO1 when mixer path 2 is activated.

The loop filter or Kv calibration is disabled by default, and is not required in the majority of applications. This calibration varies the charge pump current to compensate for changes in Kvco (MHz/V) and N with different LO frequencies. It is only necessary in applications where the VCO is tuned over a wide frequency range and the loop response needs to be tightly controlled.

This depends on what calibrations are enabled, the clock (phase detector) frequency, and the loop bandwidth. Different applications will also have different definitions of the locking time. Typically with a 52MHz clock, 200kHz loop bandwidth, and CT_CAL enabled, the lock time will be below 70µsecs after ENBL is taken high. The PLL re-lock self clearing bit (RELOK in PLL_CTRL register) can be used to reduce lock time to around 50µsecs, this removes the VCO warm up period required after ENBL is raised.

Care must be taken with these devices at frequencies around the VCO cross over points. The VCO number programmed into P1VCOSEL/P2VCOSEL has an effect on the time taken for CT_CAL and the VCO auto select process to complete.

The reference frequency, or phase detector frequency after the reference divider, will affect the phase noise within the loop bandwidth. Using a different phase detector frequency affects the divider value N and the amount of noise multiplication in the loop. With a lower phase detector frequency the higher the phase noise will be. The noise is proportional to N², since it follows 20log₁₀(N) law. The fact that the phase detector and charge pump noise rise with increased frequency offsets the change given by this equation. See data sheet for comparison of phase noise with 26MHz and 52MHz reference frequencies. The lowest phase noise is achieve with 52MHz.

The phase detector frequency is also used as the clock for the synthesizer calibrations, so will also affect lock time. A lower clock frequency will increase the lock time. In some circumstances it is necessary to adjust internal timer values to account for this.

When the ENBL pin is set to High, the VCO coarse tuning calibration (CT_CAL) adjusts the VCO switched capacitance until the VCO is on the correct frequency and the VCO tuning voltage is around +1.0V. This is in the middle of the op-amp output voltage range of approximately +0.2V to +2.4V.

The lock detect function uses a window detector, indicating an out of lock condition when the VCO tuning voltage is outside of a certain voltage range. When out of lock, then the LOCK bit 15 in the READBACK register will be Low. To read the LOCK bit it is necessary to first program READSEL = 0001 in the DEV_CTRL register. The lock flag can also be routed to pin 26 of the device, GPO4, by setting LOCK bit 0 in the GPO register high.

There are two windows for the lock detector:

• LD_LEV=0: 0.30V to 1.25V (narrow window)
• LD_LEV=1: 0.20V to 1.35V (wide window)

The two lock detector windows can be useful to indicate how much the VCO is drifting, and when it will be necessary to perform another CT_CAL. If with LD_LEV = 0 you get an out of lock state, this would probably indicate that the PLL is still locked, but the VCO and tuning voltage has drifted somewhat with temperature variation. This is confirmed if you get a lock indicated with LD_LEV = 1. Perform a CT_CAL to recenter the VCO.

If you get an out of lock indicated with both LD_LEV = 0 and 1, then either there is no PLL lock, or you are dangerously close to the tuning range limits. Perform a CT_CAL, by disabling and re-enabling the devicedevice or by using the PLL re-lock self clearing bit, RELOK in PLL_CTRL register.

Note that the LOCK detect function will not work with external VCOs. However a similar window detector could be used on the external VCO tuning line for example by using comparators.

The integrated op-amp can be used, but it is not recommended for two reasons. The op-amp output voltage range is only about +0.2V to +2.4V, which is not sufficient for the tuning range of most external VCOs. The noise performance of the op-amp is not low enough to give the full benefit of the low phase noise performance offered by an external VCO.

When CT_CAL has been successful then the CT_CAL result is available in the READBACK register. This register also contains a flag to indicate when the CT_CAL process has failed, CT_FAILED is bit 0. To read the CT_CAL value and CT_FAILED flag it is necessary to first program READSEL = 0001 in the DEV_CTRL register. The CT_CAL results can be useful for diagnostics since the expected CT_CAL value (0 to 127) read back for the programmed VCO frequency can be compared to expected results. There are plots of typical CT_CAL results versus VCO frequency in the datasheets, although device to device variation must be considered.

The two higher frequency VCOs (VCO2 and VCO3) overlap around 4200MHz to 4500MHz. Sometimes if the PLL is programmed to a VCO frequency in this region the PLL will not lock, since the VCO Auto Select process has failed. This is easily rectified, by changing the limits for VCO Auto Select as described below.

The VCO Auto Select process performs coarse tune calibration over each VCO in turn, and runs between the maximum and minimum CT_CAL values set in the VCO_AUTO register, CTMAX and CTMIN. With the default values the CT_CAL process sweeps from CT_CAL value of 3 to 124 (in decimal) across each VCO. This can create a small window in the calibration frequency where VCO2 and VCO3 overlap. To remove this window and get reliable CT_CAL and VCO Auto Select at all frequencies program the following values:

• VCO_AUTO (bits 7:1) CTMIN = 0000000
• VCO_AUTO (bits 14:8) CTMAX = 1111111 (127 in decimal)

The frequency error of the LO will be set by the reference source, typically a TCXO, and this error will be multiplied in the PLL. Most TCXOs have a tuning control input, which can be used to minimize frequency error. Typically a TCXO will have a frequency error of a few ppm at room temperature.

In some modes of operation the fractional-N sequence generator also causes a slight frequency offset of half an LSB (typically <0.005ppm).

The voltage-controlled oscillators within the RFFC parts operate over a frequency range of 2.7 to 5.4GHz. The fractional-N dividers and calibration circuits are not able to operate at this frequency so it is necessary to divide the output of the VCOs, using a prescaler, to a suitable frequency.

The maximum operating frequency of the calibration circuits is 1.6GHz. Therefore, if the VCO frequency is ≥3.2GHz the prescaler has to be set to /4, if the VCO frequency is <3.2GHz the prescaler should be set to /2 before CT or KV calibration can be performed.

For best phase noise performance the prescaler should be set to /2, this can be done once calibration has occurred by reprogramming the divider values using the new prescaler value. The prescaler setting of /2 also gives the lowest levels of spurs related to half the LO frequency at the mixer/modulator output.

If reprogramming the prescalar after calibration is not possible, for example due to constraints on lock time, then when operating with VCO frequency ≥3.2GHz and prescaler /4 then phase noise can be reduced by changing the charge pump leakage setting PLLCPL to 011 in the LF register. This setting gives improved performance as phase detector frequency increases.

In time-switched applications this is not an issue since VCO coarse tuning is performed every time one of the mixers is enabled. For applications where the device is always on and programmed to a fixed LO frequency, the question is raised of how often to perform the coarse tune calibration. Testing the RFFC207x, RFFC507x and RFMD208x devices over temperature has shown that the synthesizer will not maintain lock over the full temperature range, with the same CT_CAL setting. It is recommended to perform the CT_CAL for every 30°C temperature change in order to maintain the loop response and maximize performance. This assumes the standard configuration with the active loop filter. The amount of VCO temperature drift and it’s effect on tuning voltage and PLL performance will depend on the programmed VCO frequency. Plots of the tuning voltage against frequency and temperature in the device datasheets demonstrate this.

To get best performance across temperature it is recommended to set P1CTVand P2CTV to 01100 (12) in registers CTCAL1 and CTCAL2.

The lock detect flag can be used to indicate when the tuning voltage has drifted significantly with temperature, and when the VCO calibration (CT_CAL) needs to be performed. The VCO calibration can be started by taking the device into standby and raising ENBL, or by using the PLL relock self clearing bit, set bit 3 in PLL_CTRL register RELOK = 1. The PLL relock will perform the calibration and subsequent PLL locking quicker, there is no time delay associated with device activation and warm up.